1. Field of the Invention
This invention relates to a method and an apparatus for saving power dissipation during the testing and evaluation of liquid crystal display LCD panels.
More particularly this invention relates to the changing of the order of backplane and segment addressing to reduce the power consumed by LCD panels.
2. Description of Related Art
Currently, liquid crystal display LCD panels are evaluated by using a checkerboard pattern displayed on the LCD panel as a worst case. This checkerboard panel display represents the worst case example for LCD panel power dissipation. The checkerboard pattern of LCD panel data 470 is shown in FIG. 4. The ones value is denoted by an ‘X’ in the LCD cell location 410. A zero value is illustrated with a blank square cell area 420 in FIG. 4. The LCD panel shown in FIG. 4 is an 8 by 8 matrix. There are 8 common or backplane addresses shown such as 430 which is an odd common address. An even common or ‘com’ address is also highlighted 440. FIG. 4 shows the com address 450. The com address line selects which row of the matrix in FIG. 4 is selected for writing to or reading from. FIG. 4 also shows the segment address 460. The segment address would select which column of the LCD panel is being written to or read from. A uniquely selected LCD panel cell is selecting by activating the combination of the appropriate segment address and com address in FIG. 4. For example, cell 420 in FIG. 4 is selected for writing to or reading from by activating com line 1 and segment line 2.
FIG. 1 shows a conventional prior art block diagram of an LCD panel display subsystem. The LCD panel 160 has segment addresses, Seg0, Seg1, Seg2, . . . Seg_n 110. These addresses are from the data output of a random access memory 140. An address control block 150 produces the read address 120 to the RAM as well as the Common or backplane connections Com0, Com1, Com2, . . . Com_n 130. As we showed in the previous discussion on FIG. 4, the segment address selects the column of the LCD panel matrix while the Com lines select the row of the LCD panel matrix.
FIG. 2 illustrates the timing diagram for the conventional RAM. The common backplane signals Com0, Com1, Com2, and Com3 210, 220.230. 240 occur sequentially every period. The timing diagram of the segment population is shown in FIG. 2. The column of the matrix is selected when the segment lines are low as we see 250, 290 in FIG. 2. During Com0 time 210, the even columns of the LCD matrix are selected via Seg0 and Seg2—250, 290. During Com1 time 220, the odd columns of the LCD matrix are selected via Seg1 and Seg3—270, 285. During Com2 time, the even columns of the LCD matrix are selected via Seg0 and Seg2—260, 275. During Com3 time 240, the odd columns of the LCD matrix are selected via Seg1 and Seg3—280, 295.
U.S. Pat. No. 6,172,661 (Imajo, et al.) “Low power driving method for reducing non-display area of TFT-LCD” describes a low power driving method for reducing non-display area of a thin film transistor liquid crystal display.
U.S. Pat. No. 6,275,209 (Yamamoto) “LCD driver” describes a liquid crystal display driver.
U.S. Pat. No. 6,137,465 (Sekine, et al.) “Drive circuit for a LCD device” discloses a drive circuit for a liquid crystal display device.